The flip chip packaging technology was introduced by IBM in the early 1960s, and this technology differs from the wire bonding technology in that the electrical connectivity between the semiconductor chip and the substrate is achieved by the solder bumps instead of the ordinary wires. The main advantage of the flip chip packaging technology lies in its capability of elevating packaging density, thus the size of the packaged components are reduced; on the other hand, the flip chip packaging technology does not require wires of longer length, and hence the electrical functionality can be improved. As a result, the industry has been employing high-temperature soldering on ceramic substrates for years, and this technology is termed as control-collapse chip connection or 4C technology. Because the demand for semiconductor components of high-density, high-speed, low-cost has increased dramatically, and a trend that calls for smaller electronic products has emerged; it has become common to place the flip chip components on a low-cost organic circuit board (for example, a printed circuit board or a substrate board), then followed by the filling of epoxy underfill resin underneath the chip in order to minimize the thermal stress resulted from the differences in thermal expansion between silicon chip and organic circuit board structure, and the phenomenon has grown exponentially.
In the current flip chip packaging technology, the surface of semiconductor integrated circuit chip is disposed an electrode pad thereof, and its corresponding connecting pads are disposed on the organic circuit board; solder bumps or other conductive solder materials are filled between the chip and the circuit board, so that the chip is disposed on the circuit board with its electrical connecting side facing downwards. The solder bumps or the conductive adhesive materials used in this technology provides for the electrical input and output, as well as the mechanical connection between the chip and the circuit board.
As shown in FIG. 1, in the flip chip packaging technology, a plurality of metal bumps 11 are formed on electrode pads 12 of a chip 13, and a plurality of preset solder bumps 14 made of solder are formed on electrical connection pads 15 of a circuit board 16, then solder joint 17 are formed by reflowing preset solder bumps 14 to the corresponding metal bumps 11 under the condition of having the temperature sufficient for melting the preset solder bumps 14. In the next step, the chip and the circuit board are coupled by using the underfill material 18, so that the integration and the reliability of the electrical connection between chip 13 and circuit board 16 can be ensured.
Moreover, when the circuit board and the semiconductor chip are to be packaged, a plurality of solder balls are required to be implanted on the bottom surface of the circuit board, so that it is possible for the circuit board to electrically connect to external electronic devices. In order to allow the solder balls to connect to the circuit board effectively, the electrical connection pads of the circuit board that are to be used for the disposition of solder balls must be formed with the solder materials for connecting the solder balls first.
Currently, the method that is most commonly used to form solder material on the electrical connection pad of the circuit board is the stencil printing technology. As shown in FIG. 2, a solder-mask layer 21 is formed on a circuit board 20 that has been wired with circuits, then a plurality of electrical connection pads 22 are exposed, so that a stencil 23 with a plurality of openings 23a are placed on the solder-mask layer 21 of the circuit board 20; solder deposition can be formed on the electrical connection pads 22 by the openings 23a (not shown in the figure). A roller 24 or spray mode can be utilized to allow the solder to accumulate in the openings 23a, and once stencil 23 is removed, the solder deposition is formed in the openings 23a. This is followed by the reflowing process, which allows the solder deposition on the electrical connection pads 22 to solidify into the solder structure.
However, the developmental trend of miniaturization for semiconductor chip is driving changes in the semiconductor packaging technology, in order to allow the ever-shrinking chips to have more input and output terminals. But the change also shrinks the total area of carried components in a chip, which in turn increases the quantity of electrical connection pad on the carried components; as a result, the demands for the development of chip can only be satisfied by shrinking the size and the pitch of electrical connection pad. But the shrinking of electrical connection pad also makes the openings on the stencil used in stencil printing technology smaller as well. As a result, the smaller openings on the stencil not only increases the cost for producing the stencil, which is resulted from difficulty in stencil production; but also hampers the later production process because the smaller opening on the stencil can be impervious to the solder material. Furthermore, apart from the requirement of accurate size of stencil in order to ensure the precision in the shaping of solder material; there are the problems of the number of times the stencil has been used and cleaned. Since the solder material is viscous, it can stick to the inner wall of openings in the stencil and accumulate as the stencil is used to print many times, and this can give rise to incorrect quantity and shape of solder material from the design specification when the stencil is used next time. Therefore, when the stencil is put to actual usage, it must be cleaned after a certain times of printing, otherwise problems like conflicting shape and size of solder material can arise and result in the production process being impeded, which lowers its reliability.
To solve the above disadvantages, the method of electroplating has been employed to form solder material on the circuit board. FIGS. 3A to 3D are figures showing the procedural steps in the method for electroplating preset solder bumps on the circuit board. As shown in FIG. 3A, a solder mask layer 31 is formed on the circuit board 30 that has electrical connection pads 300, then openings 310 are formed on the solder mask layer 31 to expose the electrical connection pads 300 of the circuit board 30. As shown in FIG. 3B, a conductive layer 32 is formed on the surface of solder mask layer 31 and its openings 310, then an electroplated resist layer 33 that is to be electroplated and formed with openings 330 is formed on the conductive layer 32, so that the conductive layer 32 covered on the electrical connection pads 300 is exposed. As shown in FIG. 3C, the electroplating process is carried out, which utilizes the conductivity of conductive layer 32 as the electrically conductive pathway during electroplating, so that solder material 34 is formed by electroplating in the openings 330 that are to be electroplated. As shown in FIG. 3D, the resist layer 33 and the portion of the conductive layer 32 covered by the resist layer 33 are removed, then followed by solder reflowing so that preset solder bumps 35 are formed on the electrical connection pads of the circuit board.
Although the above procedures can solve the problems of stencil printing described previously, the difficulty of electroplating can be increased due to minimal area for electroplating, because solder materials 34 is formed in the openings of resist layer by direct electroplating. Moreover, when solder material is formed on the electrical connection pads in the openings of solder mask layer by direct electroplating, it becomes difficult to control the height of solder material on the electrical connection pads, which can lead to problems like uneven height of conductive bumps on the surface of circuit board, and this will have serious impact on the reliability of the electrical connecting process of later circuit boards and external electronic components (especially semiconductor chips).